|
Abstract:
Hardware-in-the-Loop (HIL) is a powerful real-time testing methodology that connects physical hardware components to a simulated environment representing the rest of the system. By enabling parts of the system to be replaced with models or simulations, HIL accelerates project validation and helps identify issues earlier in the design cycle.
In this webinar, we will present a HIL solution that integrates Riviera-PRO, VUnit™, and a TySOM Zynq™ MPSoC™ FPGA board to streamline automated test execution. Through a live demonstration, we will showcase how AES Cipher designs can be efficiently verified using Aldec’s dedicated USB Bridge IP, which seamlessly links simulation in Riviera-PRO with the programmable logic in the FPGA board. Attendees will also discover how to build scalable verification environments that unify simulation and hardware execution with a single script, significantly reducing effort while improving reliability and repeatability.
Agenda:
- What is hardware-in-the-loop
- Main challenges in HIL verification
- HIL main components
- TySOM Zynq MPSoC development board overview
- Using VUnit pre_config and post_check functions
- Vivado project: AES decryption
- Aldec IP USB bridge overview
- HIL Example: End-to-End Cipher Validation
- Live demo
- Conclusion
- Q&A
| 
