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VHDL-2019 is the latest official revision of the VHDL (VHSIC Hardware Description Language) standard, formally published as IEEE Std 1076-2019 by the IEEE in February 2019.
It is an evolutionary update to VHDL-2008, focusing on improving usability, consistency, and modern design-flow integration rather than redefining the language.
VHDL-2019 modernizes the language to fix ambiguities and inconsistencies left in earlier revisions; simplify common modelling and verification tasks; improve compatibility with SystemVerilog and mixed-language environments; and make the language easier to implement and maintain in simulators and synthesizers. Of all EDA vendors, Aldec offers the most support for VHDL.
If you’re already familiar with earlier versions of the language and want to know what’s new in VHDL-2019, have a look at our four-part webinar series.
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